Kaustav Banerjee

Professor

Contacts

Department of Electrical and Computer Engineering
4151 Harold Frank Hall, University of California
Santa Barbara, CA 93106-5110

tel: (805) 893-3337
fax: (805) 893-3262
kaustav@ece.ucsb.edu

Personal web site

Carbon Nanomaterials for Next-Generation Electronics and Energy Storage/Harvesting

Two feasible ultra high-density capacitive energy storage concepts from, "Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects’’ by H. Li, C. Xu, N. Srivastava and K. Banerjee, IEEE TED, Vol. 56, No. 9, pp. 1799-1821, 2009.

Research Description

Research in the Nanoelectronics Lab at UCSB focuses on two central themes:
(i) Emerging issues in nanoscale CMOS technologies and their implications for circuits and systems
(ii) Modeling, design, and fabrication of nanomaterials for next-generation electronics and energy harvesting/storage applications.

>>Specific areas of emphasis within the first theme include:
(a) Robust circuit design and design automation techniques under increasing variability and leakage
(b) Ultra high-frequency interconnect modeling and parasitic extraction techniques
(c) Innovative device-circuit-architecture co-design and optimization for overcoming end-of-roadmap CMOS limitations such as leakage and electrostatic effects
(d) Innovative low-power and ultra low-voltage circuit design

>>Research areas under the second theme include:
(a) Emerging nanotechnologies (carbon nanotube, graphene, nanowire, etc) for VLSI applications; 3-D ICs and More-than-Moore technologies
(b) Modeling and simulation framework for emerging nanoelectronics
(c) Green electronics--materials, devices, circuits, and architecture
(d) Energy storage and harvesting with emerging nanomaterials

Research Groups

• Nanoelectronics Research Lab (NRL)

Biography

Kaustav Banerjee received the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California-Berkeley in 1999 working with Prof. Chenming Hu. In July 2002, he joined the Faculty of the Department of Electrical and Computer Engineering at UCSB as an assistant professor, received tenure in 2004 and attained full professorship in 2007. He was with Stanford University during 1999-01 as a Research Associate at the Center for Integrated Systems. From February to August 2002 he was a Visiting Faculty at the Circuit Research Labs of Intel, Hillsboro, OR. In the past, he has also held summer/visiting positions at Texas Instruments Inc., Dallas, TX (1993-1997), and the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland (2001). Dr. Banerjee’s doctoral research at Berkeley and subsequent work at Stanford on thermal issues in integrated circuits set the foundation for Gradient Design Automation, the first company to introduce temperature-aware IC design technology in the Electronic Design Automation Industry. He has also been recognized with numerous awards and honors. His present research interests focus on nanometer scale issues in high-performance VLSI as well as on circuits and systems issues in emerging nanoelectronics. At UCSB, Prof. Banerjee directs the Nanoelectronics Research Lab and is an affiliated faculty at the California NanoSystems Institute. His research has been chronicled in over 175 journal and refereed conference papers. He has also co-edited a book titled Emerging Nanoelectronics: Life with and after CMOS (Springer—Verlag, 2004) and coauthored two book chapters on 3-D integrated circuits. Prof. Banerjee has served on the technical program committees of several leading IEEE and ACM conferences including IEDM, DAC, ICCAD and IRPS. He has also served on the organizing committee of ISQED at various positions including Technical Program Chair (2002) and General Chair (2005). From 2005-2008 he served on the IEEE EDS Nanotechnology Committee. Currently, he serves on the IEEE/EDS GOLD Committee and the IEEE/EDS VLSI Circuits and Technology Commitee. He is a Senior Member of IEEE and is listed in Who’s Who in America (since 2003) and Who’s Who in Science and Engineering (since 2005). Since 2008, he has been a Distinguished Lecturer of the IEEE Electron Devices Society.

Awards/Honors

• Keynote Address, International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, 2009
• Distinguished Lecturer Award, IEEE Electron Devices Society, 2008
• Finalist, IEEE/ACM William J. McCalla ICCAD Best Paper Award, 2008
• IBM Faculty Award, 2008
• Keynote Address, 12th IEEE Signal Propagation on Interconnects, Avignon, France, 2008
• IEEE-Micro Top Picks Award, 2006
• Best Paper Nominee, IEEE International Symposium on Low Power Electronic Design (ISLPED), 2005
• Outstanding Student Paper Award, 22nd VLSI Multilevel Interconnection Conference, 2005
• Research Award, Electrostatic Discharge Association (ESDA), 2005
• ACM SIGDA Outstanding New Faculty Award, 2004
• First Prize, UC Davis Business Plan Competition, 2002
• Runner Up, Stanford University Business Plan Competition, 2002
• Best Paper Award, IEEE/ACM Design Automation Conference (DAC), 2001

Selected Publications

• Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects, IEEE Transactions on Electron Devices, Vol. 56, No. 9, 2009, pp. 1799-1821, Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee, web link
• Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects, IEEE Transactions on Electron Devices, Vol. 56, No. 8, 2009, pp. 1567-1578, Chuan Xu, Hong Li, and Kaustav Banerjee, web link
• A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies, IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, 2008, pp. 1488-1498, Sheng-Chih Lin and Kaustav Banerjee, web link
• A Statistical Framework for Estimation of Full-Chip Leakage Power Distribution under Parameter Variations, IEEE Transactions on Electron Devices, Vol. 54, No. 11, 2007, 2930-2945, Hamed F. Dadgour, Sheng-Chih Lin and Kaustav Banerjee, web link
• A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs, IEEE Transactions on Electron Devices, Vol. 49, No. 11, 2002, 2001-2007, Kaustav Banerjee and Amit Mehrotra, web link
• Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, 2002, pp. 904-915, Kaustav Banerjee and Amit Mehrotra, web link
• 3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration, Proceedings of the IEEE, Vol. 89, No. 5, 2001, pp. 602-633, Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat, web link
• Global (Interconnect) Warming, IEEE Circuits and Devices Magazine, No. 9, 2001, pp. 16-32, Kaustav Banerjee and Amit Mehrotra, web link